On the Fence for IPC Certification?
Senior Electrical Engineer
Do you design, build, or test electronics assemblies? Are you thinking about IPC certification? I’ll share my experience with this program so you can decide if it makes sense for you or your team to get certified.
IPC, the Association Connecting Electronics Industries, is an ANSI organization that publishes popular standards for the electronics industry. I just completed their Certified Interconnect Designer (CID) Program. It was a 4-day commitment and cost about $2k. I learned about the conventions of the industry. This knowledge will not only help me reduce risk and increase success during tight timelines, but also better optimize the performance to price ratio of our PCBs design and fabrication process. It was well worth the investment.
For the last 5 years, I have been an electrical engineer at 219 Design, where we practice interdisciplinary product development. I’ve had the opportunity to work on projects involving software, hardware, mechanical engineering, and embedded systems. For electrical engineers, it is common for PCB layout education to be on-the-job, so I was excited to take take part in a formal comprehensive course like IPC Certification.
“You’re only kidding yourself if you put creativity before craft.”
~Twyla Tharp, The Creative Habit
IPC’s Guiding Principles
Standards Should Not
- Focus on end product performance
- Include a feedback system on use and problems for future improvement
- Show the relationship to Design for Manufacturability (DFM) and Design for the Environment (DFE)
- Increase time-to-market
- Tell you how to make something
- Contain anything that cannot be defended with data
Six Biggest Takeaways from the CID Certification Program
- Learn About the Dimension Detail on Fab Drawing
- Datums are key. Z plane is primary, X is secondary, and Y is tertiary. Also, point of origin is intersection of secondary and tertiary datum.
- Most material condition: pin size nominal + tolerance WITH hole size nominal + tolerance.
- Least material condition: pin size nominal – tolerance WITH hole size nominal – tolerance.
- Hear Fab Best Practices
- Allow your vendor maximum flexibility in fabrication.
- Maximize tolerances.
- Don’t specify a minimum hole drill size, except where current carrying capacity is critical.
- Try to allow maximum stack flexibility except where required for performance (e.g. current carrying capability, bow and twist, dielectric loss, RF, Tg).
- Allow vendor to use the stock and processes which they are most familiar, this reduces time and cost.
- Become Familiar with the Vocabulary
- Through – ol’ trusty
- Blind – extend only to one surface
- Buried – extend only between internal layers
- Microvias – aspect ratio <= 1:1, depth <= 10 mil (previously defined as < 6 mil dia., revised 2013)
- Annular Ring – Pad OD to plated ID for top or bottom layer, but PAD OD to PAD ID for an inner layer
- Nonfunctional Lands – lands on internal layers that do not make electrical connection. However, they should be included for all plated through holes, except where there is insufficient manufacturing clearance, typically such as on power or thermal planes.
- Where PCBs have many layers, it is advised to remove nonfunctional lands in the vertical stack on alternate layers.
- Expand Your Knowledge of Board Types and Performance Classes
- Board types include: single-sided, double-sided, multilayer, multilayer with blind or buried vias, multilayer metal-core, multilayer metal-core with blind or buried vias
- Performance classes are used to communicate with the manufacturer. The performance class can be related to the end-use environment and market sectors, informing the material and process selection (e.g. laminates, conformal coating, component adhesives).
- Understand the Fabrication Process – Sequence for a 2 Layer PCB, starting from laminate (your process may vary)
- Drill or laser hole: Deburr – remove burrs, Desmear – removes resin, Etchback – removes resin to improve electroless plating (rare)
- Electroless copper plating, very thin copper which seeds the electroplate
- Plate resist application: masking before electroplate (if pattern plating, else panel plating would mean no resist and entire surface plated)
- Electroplate, copper for vias
- Remove plate resist
- Etch resist application, masking before etching
- Resist removal
- Solder mask application
- Surface finish
- Identify the Enemy
- Every temperature excursion reduces circuit life.
- Mixing RoHS and leaded may mean RoHS parts experience two high temp excursions.
- Coefficient of thermal expansion: FR4 X / Y axis 12-16 ppm, FR4 Z axis: 85 ppm (driven by epoxy, perpendicular to the weave causes via cracking)).
- Tg transition (glass transition) is a bit misleading. The transition is the epoxy turning from hard to soft, actual glass has a transition temperature of ~500C.
What did I get from my CID certification?
- Listing in CID/IPC certification registry
- Learnings about DFX: Design for excellence, this is catch-all for DFM, DFA, DFT, etc.
- Understanding of the manufacturing process, hazards and acceptability standards
- Better ability to understand others’ designs, especially the vernacular of the standards
The Bottom Line
Familiarity with standards reduces risk and development time. Many common problems have been reviewed in committee, so why not learn what they decided? The CID/IPC certification includes two courses, the first course is encyclopedic and required before attending the more theoretical CID+. The content may not be helpful for someone with less than 1 year of PCB design, and I wouldn’t recommend it for non-technical managers.
So, you might want to consider taking this class because it is really informative – or maybe just reach out to 219 and we can work together to make your electronics assemblies a success!
Date published: 09/10/2017
Assembly Drawing for an Internal Development Board